A 64-thread simultaneous multi-threaded processor uses architecture and implementation techniques to achieve high throughput at low power. Included are static VDD scaling, multi-voltage design, clock gating, multiple V DD devices, dynamic thermal control, eDRAM and low voltage circuit design. Power is reduced by >50% in a 428 mm 2 chip. Worst-case power is 65 W at 2.0 GHz, 0.85 V.
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Johnson et al. (2010) studied this question.
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