Enhancing Linearity and Efficiency in Multi-Bit MAC Computation for Convolution in DNNs Using SRAM Array

This paper introduces a novel method to enhance the linearity of the multi-bit Multiply and accumulate (MAC) operation for reliable and energy-efficient convolution computation in binary-weight deep neural networks (DNNs) using static random-access memory (SRAM). We systematically analyze factors influencing linearity and inconsistency in multi-row read and write operations for analog In-Memory computation at 45 nm technology. The proposed approach employs a current mirror based approach with voltage modulated word line triggering to improve linearity in multi-bit dot product computation for MAC. With CM, linearity improves by 80% and performance analysis demonstrates a 33% enhancement in power dissipation in the proposed design.