RISC-V Graphics Rendering Instruction Set Extensions for Embedded AI Chips Implementation

In this paper, we present graphics rendering instruction extension to RISC-V ISA. In order to achieve high performance at low power consumption, the fragment rendering process is designed to be fixed-pipeline. The proposed system on a chip (SOC) is fabricated into a 3.5 × 3.5 mm2 chip using 110-nm CMOS technology. The RISC-V core with programmable vertex engine consumes 1.10 mm2 and runs at 102 MHz. The fragment engine consumes 7.44 mm2 and runs at 200 MHz. Experiment Results show that the whole chip only consumes 20 mW at full speed, and the performance per milliwatt is over 200 times more than modern MCU chip with GPU core.