Integration of clock skew and register delays into a retiming algorithm

The clock frequency of a synchronous circuit can be increased by retiming, an operation of temporally and physically relocating the registers. A new approach to the retiming process is presented which enables one to consider the effects on optimal retiming of electrical issues such as variable clock distribution delays and different register delays due to variable loads and cell instances. The algorithm provides increased accuracy in determining the maximum clock frequency and also eliminates any race conditions. Depending on the nature of the synchronous circuit, retiming using this algorithms may also provide an increase in system operating clock frequency.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>