Optimal choice of intermediate latching to maximize throughput in VLSI circuits

This paper investigates the optimal tradeoff between the degree of intermediate latching and cost in special-purpose VLSI chips, using the measure AP, where A is the chip area and P is the period (the reciprocal of throughput). The results show that significant reductions in AP-product (reciprocal of throughput per unit area) can be achieved by-intermediate latching in many typical signal processing applications, for a wide range of circuit parameters.