65k-neuron integrate-and-fire array transceiver with address-event reconfigurable synaptic routing

We present a mixed-signal VLSI event-driven neural array with 65k two-compartment integrate-and-fire neurons each with four time-multiplexed facilitating conductance-based synapses. The array implements general spike-based neural models with dynamically reconfigurable synaptic connectivity through address-event routing of synaptic events. Measurements of synaptic and neural transceiver characteristics are presented, showing variation in neuronal excitability and paired-pulse synaptic facilitation with analog control parameters. The chip measures 5mm × 5mm in 130nm CMOS and consumes 252μW from 1.5V at 5M event/s synaptic input rate resulting in 50pJ/spike power consumption.