Multi-objective GA-SA (MOGASA) algorithm for TSV and thermal aware 3D IC floorplanning

In Three-Dimensional Integrated Circuits (3D IC), two or more active device layers are stacked vertically. The vertical interconnection between the layers is achieved by metal pillars called 'Through-Silicon-Via (TSV)'. It alleviates the more extended wirelength problem that exists in the conventional 2D ICs. Though the 3D IC has numerous advantages, there are a few critical issues to be addressed with respect to the number of TSVs and chip temperature. The number of TSVs required increases when the active layers in 3D IC increase. Since TSVs occupy more silicon space, the chip area and total wirelength substantially increase. The chip temperature is another severe issue in the 3D IC. Due to the heterogeneous integration, the chip temperature increases. Also, managing heat dissipation in 3D ICs is crucial due to the stacked nature of the dies, which leads to hotspots and uneven temperature distribution. High temperatures can degrade performance, reduce reliability, and increase cooling costs. Without effective thermal management, the performance of the 3D IC can be significantly compromised, leading to potential failures and inefficiencies. Many existing methods typically optimize only one or two metrics, such as wirelength or chip area, which can lead to suboptimal designs. Improving one metric without considering others can cause issues; for example, reducing wirelength might increase TSV usage, raising costs and complexity. Focusing solely on chip areas can neglect thermal issues, creating hotspots that harm performance and reliability. Thus, it is essential to use a comprehensive approach that addresses multiple design metrics for effective 3D IC optimization. Hence, this paper presents a multi-objective floorplanning optimization algorithm to minimize number of vias, and chip temperature along with traditional metrics such as chip area, and wirelength. We decompose the 3D IC floorplanning problem into multiple 2D layers, optimizing each layer separately. It reduces the complexity of the problem and makes it more manageable. This approach also breaks down the optimization task into smaller sub-problems, enhancing scalability. We innovate by employing a B*-Tree representation for layer-wise 2D floorplanning, enhancing the efficiency of module placement and minimizing inter-layer module swapping. The proposed algorithm consists of two phases: Global floorplanning through a Genetic algorithm (GA) and Local floorplanning (Layer-wise) through a Simulated Annealing (SA) algorithm. During GA, the functional modules are strategically paved on different layers, with a primary focus on optimizing the number of vias. The obtained floorplan is further optimized during SA to reduce the chip temperature. Also, our algorithm strategically places TSVs to balance the need for vertical connectivity with the goal of minimizing the silicon area occupied by TSVs. Specifically, the optimized floorplan achieved a reduction of 7.9% in wirelength, 2.9% in the number of Through-Silicon-Vias (TSVs), and an impressive 19.8% decrease in chip temperature on GSRC benchmark circuits when compared to state-of-the-art methods.