Getting to the bottom of deep submicron II

Global interconnect is commonly regarded as a key potential bottleneck to the advancing performance of high-speed integrated circuits. Previous work has suggested that local interconnect effects can be managed through a deep submicron design hierarchy that uses 50,000 to 100,000 gate modules as primitive building blocks. This work aims to examine interconnect at the global level to determine if there are any significant roadblocks which will prevent National Technology Roadmap for Semiconductors expectations regarding clock speed from being met. Specifically, the issues of global RC delay, signal time-offlight, inductance, clock and power distribution, and noise are studied. Results indicate that, while global clock frequencies will necessarily be lower than local clock speeds, NTRS expectations should be attainable to the 5O-nm technology generation. Achieving these high clock speeds (10 GHz local clock) will be aided by the use of a newly proposed routing hierarchy which limits interconnect effects at each level of a design (local, isochronous. and global).