Single-event-upset (SEU) awareness in FPGA routing

The majority of configuration bits affecting a design are devoted to FPGA routing configuration. We present a SEU-aware routing algorithm that provides significant reduction in bridging faults caused by SEUs. Depending on the routing architecture switches, for MCNC benchmarks, the number of care bits can be reduced between 13% and 19% on average with comparable delay. In addition, in Asymmetric SRAM FPGA using our router average FIT (failure-in-time) rate is reduced by 36%.