TAPCA: An Interface-Aware Cache Management Framework for Task Partitioning on CPU-FPGA SoC Platforms

CPU-FPGA SoC architectures with multiple shared coherent caches reduce inter-component communication overhead and enable efficient CPU-FPGA collaboration through task partitioning. However, existing studies primarily focus on optimizing partitioning units and ignore the benefits and diversity of coherent cache architectures on CPU-FPGA SoCs, leading to extra communication overhead in the final partitioning decisions. To address this, we propose TAPCA, a memory interface-aware task partitioning framework that integrates coherent cache management and selection. TAPCA includes an adaptive partitioning unit generator to identify essential application structures for efficient design space exploration, a design space exploration module to profile partitioning units across various design points, a memory management modeling module based on cache bypassing to match each unit with its optimal memory architecture and assess communication overhead, and a knapsack problem partitioning solver to determine partitioning decisions with appropriate configurations of hardware and memory architectures for partitioning units.