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This randomized trial demonstrates improved partitioning speed and accuracy through task graph reduction in embedded systems, suggesting a more efficient design process.
Hardware/software (HW/SW) partitioning is one of the key processes in an embedded system. It is used to determine which system components are assigned to hardware and which are processed by software. In contrast with previous research that focuses on developing efficient heuristic, we focus on the pre-process of the task graph before the HW/SW partitioning in this paper, that is, enumerating all the sub-graphs that meet the requirements. Experimental results showed that the original graph can be reduced to 67% in the worst-case scenario and 58% in the best-case scenario. In conclusion, the reduced task graph saved hardware area while improving partitioning speed and accuracy.
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Li et al. (2012) studied this question.
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