Scaling Trends for Picojoule-per-Bit WDM Photonic Interconnects in CMOS SOI and FinFET Processes

This paper presents a link analysis for optical interconnects based on CMOS scaling toward FinFET devices. An on-chip wavelength division multiplexing (WDM) link is modeled assuming silicon photonic ring modulators, WDM multiplexers and demultiplexers, and photodetectors. A high-speed CMOS transceiver is designed and evaluated using 28-nm FD-SOI and 14-nm FinFET processes. Compared to 28-nm FD-SOI, the 14-nm FinFET offers higher intrinsic gain and allows for 50% higher transconductance per drain current suggesting more energy-efficient circuit design. Cosimulation of the photonic and electronic devices demonstrates an optimum energy efficiency of ~ 2 pJ/b at 25 Gb/s for a bit-error rate of 10 -12 including laser and ring tuning power.