FPGA-Based Speed Control IC for PMSM Drive With Adaptive Fuzzy Control

The new generation of field programmable gate array (FPGA) technologies enables an embedded processor intellectual property (IP) and an application IP to be integrated into a system-on-a-programmable-chip (SoPC) developing environment. Therefore, this study presents a speed control integrated circuit (IC) for permanent magnet synchronous motor (PMSM) drive under this SoPC environment. First, the mathematic model of PMSM is defined and the vector control used in the current loop of PMSM drive is explained. Then, an adaptive fuzzy controller adopted to cope with the dynamic uncertainty and external load effect in the speed loop of PMSM drive is proposed. After that, an FPGA-based speed control IC is designed to realize the controllers. The proposed speed control IC has two IPs, a Nios II embedded processor IP and an application IP. The Nios II processor is used to develop the adaptive fuzzy controller in software due to the complicated control algorithm and low sampling frequency control (speed control: 2 kHz). The designed application IP is utilized to implement the current vector controller in hardware owing to the requirement for high sampling frequency control (current loop: 16 kHz, pulsewidth modulation circuit: 4-8 MHz) but simple computation. Finally, an experimental system is set up and some experimental results are demonstrated.