System-level modeling of microprocessor reliability degradation due to TDDB

Time-dependent dielectric breakdown (TDDB) is leading reliability concerns for modern microprocessors. In this paper, a framework is proposed to analyze the impact of TDDB on state-of-art microprocessors and to estimate microprocessor lifetimes due to TDDB. Our methodology finds the detailed electrical stress and temperature of each device within a microprocessor system running a variety of standard benchmarks. Combining the electrical stress profiles, thermal profiles, and device-level models, we do timing analysis on the critical paths of a microprocessor using our methodology to characterize microprocessor performance degradation due to TDDB. In addition, we study DC noise margins in conventional 6T SRAM cells as a function of TDDB degradation to provide insights on reliability of memories embedded within microprocessors under realistic use conditions.