A VLSI systolic adder for digital filtering of delta-modulated signals

A fully systolic VLSI architecture allowing addition of N sequentially available input numbers is presented. It consists of a bit-level systolic adder, systolically resettable, which accumulates the partial sums, and of a systolic control network which provides the correct signs of the input data. This architecture has all the advantages of systolic arrays, such as concurrence of calculations and ease of expansion, and it is really simple to design because the complexity of the cells used is comparable to that of a half adder. In addition, the delay introduced by the slowest cell is quite small and, as a consequence, the data throughput can be considered much higher than in other solutions. Furthermore, by introducing a useful mathematical notation, the correctness of the structure is proved.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>