With the arrival of the multimedia era, high-data-rate memory LSIs are becoming increasingly important to keep up with high-speed CPUs, graphics processors, and other consumers of stored data. Video editing and replaying of high-definition television in particular require a high bandwidth. This paper presents two circuit technologies for a synchronously operating high-data-rate 1 Gb DRAM: a distributed-column-control architecture reducing the burst-mode cycle time, and a ringing-canceling output buffer ensuring reliable high-speed data transfer.
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Horiguchi et al. (2002) studied this question.