Building packet buffers using interleaved memories

High end routers need to store a large amount of data. Dynamic random access memories (DRAMs) are typically used for this purpose. However, DRAM memory devices don't match the bandwidth requirements, especially in terms of random access speeds. In this paper, we analyze a generalized memory interleaving scheme. This scheme implements a large, fast memory using multiple, slower DRAMs. In the presence of small amount of speed-up, we show that reasonable statistical guarantees (i.e., low drop probabilities) can be provided by using small SRAM buffers that queue read/write requests to DRAMs. We then relate drop probabilities to SRAM buffer size for a wide range of statistical arrival patterns.