Experimental research verifies the impact of interconnect variation on circuit performance across technologies, indicating significant effects below 10 nm design.
As the feature size of integrated circuits decreases, interconnect delay has become one of the major factors on performance. This research was conducted to verify the delay impact of interconnect variation throughout technology scaling. Process variations and timing models are considered simultaneously at various semiconductor technologies. Experimental results show the interconnect variation has a great effect on circuit performance especially below 10 nm design.
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Jin et al. (2022) studied this question.
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