Robust 7-nm SRAM design on a predictive PDK

SRAMs are ubiquitous in modern VLSI design but have become difficult to design in advanced finFET processes due to fin quantization and large variability at small geometries. In this paper six transistor SRAM design on a 7-nm predictive PDK is presented. The SRAMs use differential sense amplifier based sensing to support long bit-lines and high array efficiency. Different SRAM cells are evaluated statistically, resulting in the choice of a 122 cell due to its easier lithography and superior write margins. A novel switched capacitor reduced column VDD is presented, which has excellent across corner voltage characteristics and speed. The analysis shows yield to a minimum VDD of 500 mV.