A bit-parallel, word-parallel, massively parallel associative processor for scientific computing

A simple but powerful parallel architecture based on the classical associative processor model, which allows bit-parallel computation and communication, is proposed. Complex operations such as multiplication execute in O(m) cycles, as opposed to O(m/sup 2/) for bit-serial machines. This permits very fast processing of floating-point data. A bit-parallel communication network that exploits associative data location independence is presented. It provides the system with a reconfiguration capability, which improves chip yield, as well as fault tolerance. The simplicity of the architecture lends itself to VLSI implementation and hence allows the construction of a bit-parallel, word-parallel, and massively parallel (P/sup 3/) computing system.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>