Key result
A fault ordering technique using information about hard-to-detect faults extracted from an untestable identification phase reduced pattern counts in SAT-based dynamic test compaction.
A fault ordering heuristic based on hard-to-detect faults can reduce pattern counts in SAT-based dynamic test compaction for post-production chip testing.
Each chip is subjected to a post-production test after fabrication. A set of test patterns is applied to filter out defective devices. The size of this test set is an important issue. Generally, large test sets increase the test costs. Therefore, test compaction techniques are applied to obtain a compact test set. The effectiveness of these technique is significantly influenced by fault ordering. This paper describes how information about hard-to-detect faults can be extracted from an untestable identification phase and be used to develop a fault ordering technique which is able to reduce the pattern counts of highly compacted test sets generated by a SAT-based dynamic test compaction approach.
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Eggersglüß et al. (2014) studied this question. Fault ordering heuristic was evaluated on Pattern counts of highly compacted test sets. A fault ordering technique using information about hard-to-detect faults extracted from an untestable identification phase reduced pattern counts in SAT-based dynamic test compaction.
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