Hierarchical performance optimization for synthesis of linear analog systems

This paper presents a hierarchical performance optimization method for high level synthesis of analog systems. The goal is to minimize silicon area while meeting design constraints i.e. AC behavior, op amp gains, slew-rate, power etc. The technique is organized as two successive steps: (1) gain distribution for assigning gains to circuits; and (2) actual performance optimization for finding design parameters that minimize area, realize the assigned circuit gains and meet imposed design constraints. Our experiments show that the proposed method successfully synthesizes analog designs such as filters or communication systems in a reasonable length of time.