High-Speed Serial AER on FPGA

The paper presents a high speed serial address-event representation (AER) link with a capacity of 41.66Mevents/sec. The link has been implemented using a low voltage differential signaling (LVDS) interface on a commercial FPGA. Many of the latest reconfigurable devices (FPGAs, CPLDs, etc.) offer highly optimized modules for this kind of communication. However, many AER processing systems require an ASIC implementation. The paper proposed to implement AER components with a serial AER interface as multi-chip PCBs with one or several ASICs communicating in parallel with an FPGA that handles the external high speed serial link. The authors judge the design effort to be much smaller than in a comparable monolithic ASIC implementation.