A 14b three-stage ADC uses a complementary bipolar process to achieve a 100MSample/s encode rate with a SFDR of >90 dB and an SNR of 75 dB. While the design is based on a traditional multi-stage architecture, the three encoder stages use serial-ripple converters. Unlike the typical N-bit flash converter which requires 2-/sup N-1/ comparators, the serial-ripple converter has only N comparators. The result is a smaller die area and lower power dissipation than flash. This design uses a total of 16 comparators, and at the full sample rate consumes 1250 mW. It is fabricated in a 0.8 /spl mu/m double-poly complementary bipolar process.
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Moreland et al. (2002) studied this question.