Bounding Worst-Case Access Times in Modern Multiprocessor Systems

When evaluating worst-case execution times of real-time software on an off-the-shelf multiprocessor system, one should consider the architecture of the underlying hardware. This paper evaluates and discusses the impacts of the chipset of a symmetric multi-processing (SMP) architecture on the execution times of software. It will show how one can obtain worst-case execution times of accesses to main memory and to peripheral devices. This paper also introduces parameters to describe the different impacts on these access times. These parameters reflect the worst-case execution times of a set of uninterrupted accesses at different load conditions. Depending on the real-time requirements, accesses to main memory or to peripheral devices can be performed at different configuration states of hardware. At each state, the worst-case access times differ. This paper shows how these access times can be used for the evaluation of worst-case execution times of real-time software.