A 4 Mb 1T1C FeRAM with a common-plate folded bit-line architecture achieves low noise without cell area penalty in nonvolatile ferroelectric RAM. The decoder of common plate scheme reduces area to about 62% that of a conventional separate-plate scheme. The chip area is reduced by 9.2% to 111 mm/sup 2/. The bit-line capacitance imbalance is resolved without speed loss or area penalty.
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Jeon et al. (2002) studied this question.