Optimizing FPGA and Wafer Test Coverage with Spatial Sampling and Machine Learning: Analysis of Local Spatial Consistency

Wafer and FPGA testing remains costly in semiconductor manufacturing. This paper studies random sampling, stratified sampling, and k-means sampling under a partial-measurement setting with Gaussian Process Regression (GPR), and introduces Short Distance Elimination (SDE), a spatial screening rule that spreads selected training points over the layout. Combining value-based sampling with SDE yields two hybrid methods: S-SDE, which applies SDE within stratified subsets, and K-SDE, which applies SDE within k-means clusters. A calibration-based protocol fixes the value-group labels and SDE thresholds before target-file prediction. The SDE thresholds are selected from (α,β) configurations in {0,1,2,3,4}, excluding (0,0), using local window statistics and RMSD-based calibration sweeps. Both wafer and FPGA calibration files support (α,β)=(2,2), which is then fixed for all remaining experiments. Experiments on industrial wafer data and actual FPGA silicon data, repeated across four random seeds, show that K-SDE reduces RMSD by 15.84% for wafer data and 13.03% for FPGA data relative to k-means sampling, while S-SDE reduces RMSD by 16.26% and 8.63% relative to stratified sampling.