Design and Simulation of a High-Throughput RISC-V Processor with Parallel Cryptographic Execution Units

This project presents the design and simulation of a high-performance RISC-V processor integrated with parallel cryptographic execution units to enhance data security and computational throughput. A 32-bit pipelined RISC-V architecture is implemented with a custom instruction extension dedicated to cryptographic operations. Unlike conventional designs that execute encryption sequentially, the proposed system incorporates multiple parallel crypto units within the execute stage, enabling simultaneous processing of multiple data blocks. The architecture employs four parallel encryption modules operating concurrently on different input data, while a selector mechanism dynamically routes outputs to the writeback stage. This design significantly improves throughput by achieving multiple encryptions per clock cycle without increasing latency. Functional verification is performed using behavioural simulation in Vivado, where waveform analysis confirms correct operation of instruction flow, parallel execution, and output selection. Performance evaluation demonstrates that the proposed design achieves up to 4x improvement in throughput compared to traditional single-unit cryptographic implementations. Additionally, encryption and decryption validation ensures correctness and reliability of the system. The project highlights the effectiveness of integrating parallel processing techniques within a RISC-V processor for secure and efficient embedded system applications.