Investigating the impact of gate stacks on ALD IGZO transistors via source/drain contact characterization

Achieving co-optimization of performance and bias stability is crucial for enabling broader applications of indium-gallium-zinc oxide (IGZO) transistors in next-generation electronics. In this work, back-gate IGZO transistors with different gate stacks are systematically characterized to elucidate the role of interfacial layers (ILs) between the IGZO channel and the HfO2 insulator in device performance and bias stability. The transistor with the HfO2/ZrO2 stack exhibits a near-zero threshold voltage of −0.02 V and a low subthreshold swing of 75.2 mV/dec, outperforming counterparts with HfO2 or Al2O3 ILs. Driven by the larger chemical potential gradient at the IGZO/HfO2 interface, the IGZO film deposited on the HfO2 stack contains the highest concentration of oxygen vacancies (OVs). A large fraction of induced OVs structurally relax into deep-level traps that pin the Fermi level (EF) and impede electron injection at source/drain (S/D) contacts. In contrast, the IGZO films on ZrO2 and Al2O3 ILs exhibit substantially lower OV concentration and thus weaker EF pinning, resulting in reduced S/D contact barriers. Bias stress stability measurements further highlight the critical importance of both robust gate stacks and stable IGZO/high-k interfaces. Ultimately, this gate stack engineering offers a feasible pathway to fabricate high-performance and reliable IGZO transistors for advanced applications.