Spare-Row-Based Fault-Tolerant Dynamic Operation Units for RRAM Computing-in-Memory Systems

Resistive random-access memory (RRAM) crossbar architectures are constrained by the limited number of word lines that can be activated simultaneously, thereby restricting the degree of parallelism achievable in computing-in-memory systems. To alleviate this architectural bottleneck, dynamic operation units have been proposed; however, existing implementations generally lack fault tolerance support, leading to significant yield degradation in the presence of defective memory cells. A recent study employed spare rows to provide fault tolerance, but such an approach is fundamentally limited by the number of available spare rows. In contrast, this paper proposes a generalized fault-tolerant scheme that is independent of the number of spare rows. To enable flexible row remapping, a novel word line activation generator are introduced. Experimental results demonstrate that the proposed architecture provides effective fault tolerance while incurring only minimal area and power overhead.