Demonstrates improved binary portability in RISC-V architectures, indicating enhanced software longevity.
RVV (RISC-V Vector Extension) provides a flexible and scalable vector architecture that enables high performance across multiple domains. However, the continuous evolution of the RVV specification, from early drafts to the ratified v1.0, has led to notable ISA (Instruction Set Architecture) fragmentation, which poses persistent challenges to the longevity and portability of compiled software. In particular, binaries produced for one ISA version often fail to execute correctly on hardware supporting another ISA version, thereby undermining both software portability and hardware reuse. To bridge this gap and enrich the RISC-V software ecosystem, this paper presents RVV-Morpher, a semantic-aware static binary rewriting framework that enables portability across binaries targeting different RVV versions. Operating directly at the binary level, RVV-Morpher preserves program correctness and generates efficient code by decoding, analyzing, optimizing, and reconstructing vector instructions to bridge differences in encoding and semantics. This paper illustrates RVV-Morpher’s translation from RVV v1.0 to RVV v0.7.1, the most practically relevant case given the wide deployment of RVV v0.7.1 hardware and the maturity of the RVV v1.0 toolchains. In our evaluation on the TSVC_2 benchmark, RVV-Morpher achieved significant speedups compared to native RVV v0.7.1 binaries across most loop categories, with a geometric-mean speedup of 1.43 × and peak improvements of up to 3.07 × in certain categories. On the RiVEC benchmark, RVV-Morpher successfully translated all 10 data-parallel applications, maintaining stable efficiency across different input sizes with a geometric-mean speedup of 1.24 ×.
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Zou et al. (2026) studied this question.
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