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This letter presents an ultra-low OP1dB buffer LNA for signal level control at the ADC interface, indicating potential improvements in receiver design.
To prevent potential damage to ADC input circuitry from excessive RF front-end output signal strength in modern receivers, this letter presents an ultra-low OP1dB wideband buffer LNA for signal level control at the ADC interface. Designed with an adjustable low-gate-voltage bias, negative feedback, and current-reuse techniques, the LNA was fabricated in a 0.15-μm GaAs pHEMT process. An average gain of 19.5 dB is measured across 1–6 GHz, with average OP1dB of -0.4 dBm and average OIP3 of 11 dBm. The chip occupies 1.5×1.0 mm2.
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Wang et al. (2026) studied this question.
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