Early access to accurate congestion information can effectively optimize the physical design flow of modern very large scale integration (VLSI) circuits. Existing unimodal models suffer from limited feature utilization and insufficient prediction accuracy, while current multimodal approaches typically involve large parameter sizes, slow inference, and high computational complexity, making them difficult to apply in time-critical tasks. To address these limitations, we propose CGNet, a novel lightweight multimodal model for congestion prediction that simultaneously processes feature maps and heterogeneous graphs. To enable efficient feature fusion without significantly increasing model complexity, we incorporate a cross-stitch module. Furthermore, we propose a heterogeneous graph compression method that significantly simplifies the graph structure, thereby reducing the computational complexity of processing heterogeneous graphs and improving the prediction speed of the model. Additionally, we design a composite loss function that jointly captures global structures and local details. For a more comprehensive evaluation, we propose a localized metric, intersection over union (IOU), and integrate the predicted congestion maps into the downstream design rule check (DRC) violation prediction task. Experimental results in the CircuitNet-N28 dataset demonstrate that CGNet consistently outperforms the best-performing model in both prediction accuracy and prediction speed.
Y et al. (Fri,) studied this question.