Investigation of TMDC-based impact-ionization field effect transistor (I2-FET) for low power logic

To overcome the challenges of power dissipation and short-channel effects (SCEs) driven by continuous semiconductor dimensional scaling, impact-ionization field-effect transistors (I 2 -FETs) based on a transition metal dichalcogenides (TMDC) material channel have emerged as highly promising candidates for next-generation low-power applications. To employ such steep-switching devices in logic applications, extensive research efforts have been continuously devoted to the I 2 -FET. However, prior studies have predominantly focused on the direct-current (DC) I-V switching characteristics at the single-device level, while capacitance–voltage (C-V) characteristics — which are equally critical for circuit-level operation — have remained largely unexplored despite their growing importance. This study therefore provides a comprehensive analysis spanning both I-V and C-V characteristics of the I 2 -FET and evaluates their combined impact on logic circuit performance. I-V characteristics reveal that the device exhibits an exceptionally steep subthreshold swing (SS) well below the Boltzmann limit and a high on-current, both enabled by the impact ionization mechanism, while maintaining a low off-current owing to the potential barrier at the junction. C-V characteristics exhibit anomalous gate capacitance behavior caused by an abrupt increase in carrier multiplication during device turn-on. However, circuit-level evaluation using a complementary metal-oxide-semiconductor (CMOS) inverter demonstrates for the first time that the dramatic enhancement in drive current induced by impact ionization plays a more dominant role in determining the overall switching delay than the detrimental impact of the anomalous gate capacitance. In conclusion, for the application of WSe 2 I 2 -FET in integrated circuits, maximizing the drive current through the optimization of contact properties and dimensional parameters, such as the ungated length (L ungated ) and gated length (L gated ), are significantly more important than merely controlling the C-V characteristics. This study thus provides comprehensive design guidelines for future low-power logic circuits.