Design Insights of Nanosheet FET and CMOS Circuit Applications at 5-nm Technology Node

In this article, FinFET, vertically stacked gate-all-around (GAA) nanowire (NW), and nanosheet (NS) FETs performance are estimated with equal effective channel widths ( <tex-math notation="LaTeX">Weff </tex-math> ) at the 5-nm technology node (N5). The comparison reveals that NS FET exhibits the highest ON current ( <tex-math notation="LaTeX">ION </tex-math> ), the lowest OFF current ( <tex-math notation="LaTeX">IOFF </tex-math> ), and the largest <tex-math notation="LaTeX">ION/IOFF </tex-math> ratio with better subthreshold performance. We also explore the geometrical variation of the NS FET toward better dc and analog/RF applications and outlined the necessary design guidelines. Moreover, the robustness of NS FET for temperature variations is also performed and analyzed. Finally, the effect of NS width ( <tex-math notation="LaTeX">NSW </tex-math> ) on common source (CS) amplifier, CMOS inverter, and ring oscillator circuits is performed by the Verilog-A model in the CADENCE simulator. An increment of 45.11% in oscillation frequency ( <tex-math notation="LaTeX">fosc </tex-math> ), 155.5% rise in CS amplifier gain, <tex-math notation="LaTeX">2.5× </tex-math> increment in energy-delay product (EDP), and marginal reduction in inverter noise margin (NM) is noticed with larger <tex-math notation="LaTeX">NSW </tex-math> . From the result analysis, it is noticed that for sub-5-nm technological nodes, NS FETs exhibit superior performance and ensure fundamental scaling.