Real-Hardware Deployment of a Nussbaum-Function PID Controller on a Current-Controlled Low-Cost Actuator via Hardware-Aware Optuna Tuning

Real-hardware deployment of adaptive manipulator controllers remains difficult because assumptions made in paper-level formulations are weakened by friction, encoder quantisation, current limits, communication latency, and low-speed actuation nonlinearities. This paper investigates that deployment gap for a recent Nussbaum-function PID controller by translating it from a simulation-level formulation into direct current-command control on a Niryo NED3 Pro actuator. To isolate deployment-layer behaviour from the whole-arm Coriolis, centrifugal, and gravity dynamics, the study is centred on a single decoupled actuator (Dynamixel ID 6, distal wrist) under long-horizon sinusoidal tracking around a fixed operating region. A direct transfer of the baseline law is first reproduced and shown to degrade through cumulative adaptation-state growth, weakening of the Nussbaum modulation, and high internal command saturation. A hardware-oriented implementation is then evaluated that preserves the Nussbaum core while adding adaptation-state regularisation, low-speed velocity-reference feedforward, and tail-region damping; its parameters are selected through a hardware-aware Optuna archive of 79 real-hardware trials with hard rejection of unsafe runs and a score that jointly reflects tracking quality, internal command saturation, actuation activity, and bounded adaptation growth. Over 300 s of continuous operation, the enhanced implementation reduces the mean absolute error from 10.476∘ to 1.054∘ and the internal command saturation ratio from 0.450 to 0.012 relative to the direct baseline, within the reported actuator, trajectory, and safety envelope. The main contribution is therefore not only a tuned controller but a reproducible real-hardware methodology showing how Nussbaum-based PID control can be deployed and improved on a low-cost manipulator when adaptation management, actuation mapping, and hardware-aware optimisation are treated as core elements of the research design.