Thermal Reasoning Substrate: A Heat-Driven Shared Memory Architecture for Parallel LLM Inference

Multi-step reasoning with large language models (LLMs) is increasingly structured as parallel branch execution, where subquestions or subtasks run concurrently and their outputs are merged before a final answer is synthesized. We introduce the Thermal Reasoning Substrate (TRS), a shared compact memory architecture that replaces hard causal synchronization with soft, latency-gated dependency. TRS maintains a 128-dimensional int8-quantized entity heat map — approximately 150 KB of working memory — that all parallel branches continuously read from and write to during inference. Salience is propagated across semantic neighbors via spreading activation with configurable decay over two hops. A per-entity-type z-score gate suppresses premature forwarding of low-confidence activations. A typed value bus provides exact key-value slots for numeric and precise dependencies, supporting mid-stream early forwarding. We validate TRS on an internal SLP benchmark of 50 queries over 291 replayed transcript turns, achieving MRR 0.940, exceeding a full embedding-scan engine (MRR 0.739) by a factor of 1.27, while maintaining a fixed 150 KB working set versus the engine's O(n) memory footprint.