Dyn MM: A Dynamic Modulus-Update Memory-Based Modular Multiplier on FPGA

Modular multiplication is a core arithmetic primitive in many public-key cryptographic systems (Z = (X * Y) mod M); however, while static offline computed lookup tables remain the basis for modular multiplication in many current-day FPGA designs that use memory-based reduction techniques, these approaches do not allow for the dynamic updates of modulus for multi-party or cloud-based protocols. Therefore, we present a new architecture called Dyn MM to overcome the static constraints of memory-based multipliers while still leveraging their advantages of low area and latency. Dyn MM employs three main innovations: an on-chip Modulus Update Engine (MUE), which generates reduction tables in real time, a dual-bank P-MEM architecture to separate configuration from execution, and a zero-downtime switching mechanism for cycle-accurate handover. Demonstrations on Xilinx Virtex-7 FPGAs show that this architecture reduces modulus update latency from seconds (offline reconfiguration) to microseconds (on-chip updates) while introducing only 23% additional area overhead.