FAD‐Net: An Efficient Architecture for Defect Recognition in Semiconductor Wafers

Automatic wafer map classification and recognition remain a major challenge in the intelligent semiconductor manufacturing process. The defect category identified from a wafer map provides valuable information for tracing the primary cause to improve production quality through classification and recognition of wafer map defect patterns. In this work, a novel architecture is proposed, termed the Feature Aware Dendritic Network (FAD‐Net), for pattern recognition and multi‐class classification of complex single‐type wafer map defects. It integrates a Dendritic Neuron Module (DNM), a Feature Pyramid Module (FPM), and attention mechanisms to capture discriminative features. The three‐stage model uses a biologically inspired DNM to focus on nonlinear interactions among features, an FPM for aggregating multi‐scale features, and attention mechanisms for enhancing spatial and channel‐wise feature representations to improve the classification and recognition. Experimental results demonstrate an accuracy of 95.35%–98.63%, F1‐score of 0.9255–0.9858, and an AUC of 0.9971–0.9997 on WM‐811K and MixedWM38 datasets. Compared to state‐of‐the‐art, FAD‐Net delivers improved recognition and classification performance for wafer map defect analysis.