Zero-shot PCB Defect Classification Method via a VLM-RAG Pipeline

We propose a practical VLM-RAG pipeline for PCB defect classification under severe label scarcity. Document-grounded prompts (from inspection specs and SOPs) align a CLIP-style zero-shot classifier to the manufacturing domain, ROI-tiling amplifies localized cues at inference, and a small-sample linear probe on frozen embeddings sharpens decision boundaries with minimal labeling. On a real PCB dataset, we compare domain-tuned zero-shot, ROI-tiling zero-shot, and the linear probe. ROI-tiling yields a small accuracy gain over zero-shot but does not improve macro-F1, while the linear probe achieves a meaningful improvement in both accuracy and macro-F1 over the zero-shot baseline. The reported accuracies remain below the level required for direct deployment; however, the results indicate that combining Visual RAG, document-grounded prompts, and lightweight supervision can reduce the cost of building an initial defect-classification model in data-scarce manufacturing environments, providing a practical starting point that can be incrementally refined as more labels become available.