ABSTRACT In this study, we have conducted an in‐depth investigation into the interconnect failure mechanisms of multi‐chip modules (MCMs) resulting from integration enhancements. Specifically, a highly integrated dual‐channel receiver front end (RFE) was modeled in three dimensions using the ANSYS Parametric Design Language (APDL). This RFE comprises two silicon (Si) switch chips and two gallium arsenide (GaAs) low‐noise amplifiers. Subsequently, leveraging the theory of atomic flux divergence, finite element analysis (FEA) is utilized to predict and analyze the interconnect reliability of the MCM including different temperatures, voltages, and interconnect sizes, as well as the specific impacts of various driving forces. The experimental results elucidate the impact of each operating factor and the corresponding driving force. Moreover, this research delineates the feasible domain space for structural and operational parameters, thereby providing valuable guidance for the design of MCMs. Notably, this represents the first comprehensive exploration of interconnect reliability in MCM chips, which can be instrumental in guiding layout design and enhancing the reliability and longevity of MCM chips.
Lin et al. (Thu,) studied this question.