Reliability is an increasing concern in modern computing. Integrated circuits (ICs) form the backbone of computing devices across industries, including AI, consumer electronics, healthcare, automotive, industrial, and aerospace. While Moore’s Law has driven ICs toward smaller dimensions, higher performance, and greater energy efficiency, transistor scaling to atomic levels has exacerbated aging-related degradation mechanisms such as Bias Temperature Instability (BTI), Hot Carrier Injection (HCI), Time-Dependent Dielectric Breakdown (TDDB), Electromigration (EM), and stochastic aging-induced variations. Applications like AI training and autonomous driving demand continuous, reliable operation to minimize recovery costs and enhance safety. Additionally, the high cost of chip replacement underscores the need for extended lifespans. These challenges highlight the urgency of designing more reliable ICs as critical computing infrastructure. This survey explores aging in ICs, covering key degradation mechanisms and mitigation strategies. It provides a comprehensive overview of aging’s impact, key monitoring techniques at circuit and system levels, and circuit-level mitigation strategies tailored for digital, analog, and SRAM circuits. The survey also examines emerging software-driven approaches in design automation and aging characterization, which are transforming traditional reliability optimization. Finally, it discusses challenges and future directions to improve aging management and ensure long-term IC reliability across applications.
Shaik et al. (Fri,) studied this question.