Subthreshold Time‐Mode All‐Digital DLL With Built‐In Linearization

Subthreshold charge pump delay‐locked loops (DLLs), often favored over their all‐digital counterparts for their small silicon footprint and low power consumption, suffer from the fundamental drawback of inability to lock to low‐frequency (kHz) timing references due to the leakage‐induced phase errors in the idle state of the charge pump and the exceedingly long duration of the idle state. To combat this drawback, this paper presents a subthreshold time‐mode all‐digital DLL for low‐frequency clock generation. The large and tunable delay of the DLL is obtained using a static inverter delay line whose supply voltage is in the vicinity of 100 mV and adjustable by varying supply voltage. The phase error of the DLL is processed by a time‐mode proportional block (pBlock) implemented using a delay line time‐to‐digital converter (TDC) for rapid phase error correction and an integral block (iBlock) implemented using a bidirectional gated delay line time integrator for static phase error elimination. The delay line is powered by a subthreshold voltage generator whose output is controlled by the pBlock and iBlock. The transfer characteristics of the voltage generator are profiled as per the opposite of the delay line, such that a linear relation between the tuning bit of the supply voltage and the delay of the delay line is obtained, thereby reinstating the intrinsic stability of the DLL with a drastically improved area/power efficiency. The proposed DLL is designed in a TSMC 130‐nm 1.2‐V CMOS technology with a reduced supply voltage of 0.6 V and analyzed using Spectre with BSIM3v3 device models. Simulation results show the DLL locks to a 100‐kHz 0–0.6‐V timing reference at FF/0.6 V/20°C, TT/0.6 V/27°C, and SS/0.6 V/60°C with no accumulated static phase error. The DLL occupies 0.00985 mm, offers a 59–200‐kHz lock range, 1.3% mean‐square‐root jitter, and consumes 198 nW.