Design of an adaptive finite impulse response filter using low error efficient approximate adder and two-stage operand trimming approximate logarithmic multiplier for WSN in IoT

In digital signal processing, specifically focusing on Finite Impulse Response (FIR) filters and their application in Wireless Sensor Networks (WSN) for IoT. FIR filters are essential components in signal processing systems, used for tasks such as noise reduction, signal enhancement and data analysis. Optimising FIR filter designs becomes essential in WSNs, where energy efficiency, precision and real-time processing are important. In this paper, design of an adaptive finite impulse response filter using low error efficient approximate adder and two-stage operand trimming approximate logarithmic multiplier for WSN in IoT environment (FIR-LEAA-TOTAM-WSN) is proposed. The FIR filter leverages Low Error Efficient Approximate Adder (LEAA) to significantly reduce critical path delay compared to traditional 1-bit full adders. This design effectively reduces noise and interference affecting WSNs, thereby reducing energy consumption, increasing the operational lifespan of WSNs used in IoT applications. The implementation of this design is carried out using Verilog, followed by synthesis through the Xilinx ISE suite with FPGA synthesis performed by Xilinx tools. The experimental outcomes show that the performance of HDP-FIR-LEAA-TOTAM-WSN approach attains low delay, higher dynamic power and low energy consumption when compared with existing methods, respectively.