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Using CMOS-compatible Pd catalysts, we demonstrated the formation of high-mobility ⟨111⟩-oriented GaSb nanowires (NWs) via vapor–solid–solid (VSS) growth by surfactant-assisted chemical vapor deposition through a complementary experimental and theoretical approach. In contrast to NWs formed by the conventional vapor–liquid–solid (VLS) mechanism, cylindrical-shaped Pd 5 Ga 4 catalytic seeds were present in our Pd-catalyzed VSS-NWs. As solid catalysts, stoichiometric Pd 5 Ga 4 was found to have the lowest crystal surface energy and thus giving rise to a minimal surface diffusion as well as an optimal in-plane interface orientation at the seed/NW interface for efficient epitaxial NW nucleation. These VSS characteristics led to the growth of slender NWs with diameters down to 26.9 ± 3.5 nm. Over 95% high crystalline quality NWs were grown in ⟨111⟩ orientation for a wide diameter range of between 10 and 70 nm. Back-gated field-effect transistors (FETs) fabricated using the Pd-catalyzed GaSb NWs exhibit a superior peak hole mobility of ∼330 cm 2 V –1 s –1, close to the mobility limit for a NW channel diameter of ∼30 nm with a free carrier concentration of ∼10 18 cm –3 . This suggests that the NWs have excellent homogeneity in phase purity, growth orientation, surface morphology and electrical characteristics. Contact printing process was also used to fabricate large-scale assembly of Pd-catalyzed GaSb NW parallel arrays, confirming the potential constructions and applications of these high-performance electronic devices.
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Yang et al. (2017) studied this question.
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