Low-Latency Multi-Kernel Polar Decoders

Polar codes have been receiving increased attention for application in beyond 5G networks. They offer low-complexity decoding algorithm and can achieve symmetric channel capacity. However, the majority of research works have focused on the codes constructed by the binary kernel ( <tex-math notation="LaTeX">2 × 2 </tex-math> polarization matrix) which bounds the code length to an integer power of 2. Multi-kernel polar codes have been proposed as a method that allows the construction of polar codes with sizes different from powers of 2 by mixing multiple kernels of different dimensions. A hardware implementation based on the successive cancellation (SC) algorithm found in the literature shows that it suffers from a long decoding latency. In this paper, we design and implement a multi-kernel decoder based on the fast-simplified SC (fast-SSC) algorithm to decrease the decoding latency. It can decode any code constructed by binary and ternary ( <tex-math notation="LaTeX">3 × 3 </tex-math> ) kernels featuring flexible code length, code rate, and kernel sequence. FPGA implementation results reveal that a polar code of length <tex-math notation="LaTeX">$N = 1536$ </tex-math> , rate <tex-math notation="LaTeX">R = 1/2 </tex-math> with Processing Element ( <tex-math notation="LaTeX">Pₑ </tex-math> ) value of <tex-math notation="LaTeX">Pₑ = 240 </tex-math> , gains 84.6% lower latency compared to the original algorithm. Also, the architecture supports polar codes constructed by purely-binary and purely-ternary kernels. A polar code of length <tex-math notation="LaTeX">$N = 1024$ </tex-math> , rate <tex-math notation="LaTeX">R = 1/2 </tex-math> , and <tex-math notation="LaTeX">Pₑ = 120 </tex-math> achieves an information throughput of 432 Mbps.