Reduced-Order Parametric Behavioral Model for Digital Buffers/Drivers With Physical Support

In this paper, we present a new behavioral model for high-speed digital output buffers/drivers. In the conceived model, the output current's relationship with the output voltage is expressed as a summation of a static nonlinearity plus linear dynamics. This separation in the model format is supported by the measurements as well as the physical structure of a general driver circuit. This approach merges the features of equivalent circuit and parametric approaches to build a reduced-order parametric behavioral model which, compared to other published models, is more adequate to describe the device's electrical behavior from transient input-output data. A simple single-step identification procedure is conceived to extract a model that proved to be stable and capable of significantly improving the simulation speed and accuracy of prediction. Finally, the resulting model is validated in a realistic signal integrity simulation setup, and is compared to transistor-level models and to the state-of-the-art input-output buffer information specification model.