SPHINCS+ is the only hash-based post-quantum digital signature scheme standardized by NIST. However, its complex multi-level structure and hash-intensive computations pose significant challenges for high-performance and efficient hardware implementations. This paper presents a high-throughput and efficient hardware architecture for SPHINCS+, supporting three security levels. Exploiting the computational characteristics of SPHINCS+ hash functions, a pipelined hash engine and an iterative hash engine are co-designed to efficiently serve different hashing workloads. The architecture further incorporates bubble-free scheduling and parallel Winternitz One-Time Signature Plus (WOTS+) node computation, thereby maximizing the utilization of the pipelined hash engine and improving resource efficiency. In addition, a merged-computation scheme for Forest of Random Subsets (FORS) trees is proposed to reduce the hardware overhead of supporting multiple security levels. Compared with the state-of-the-art design on UltraScale+, the proposed architecture improves area-time product (ATP) by \ (1. 6/1. 8\) for key generation and signing, and achieves \ (3. 8/4. 2/1. 9\) faster key generation, signing, and verification. Compared with the fastest existing implementation on Artix-7, it delivers \ (1. 2\) faster signing and verification, together with \ (1. 4\) better ATP.
Sun et al. (Mon,) studied this question.