Performance Enhancement of Tin Chloride‐Incorporated Ferroelectric Polymer‐Based Artificial Synapse for Hardware Neural Networks

With exponentially increasing data rates, the von Neumann architecture may no longer be an efficient computing technology owing to its energy efficiency limitations and memory bottlenecks. Recently, brain‐inspired computing based on hardware neural networks (HW‐NNs) has garnered considerable attention as a promising computing technology for processing large amounts of data. However, the energy efficiency of each local synaptic device in HW‐NNs remains significantly lower than biological synapses. Hence, we introduce a highly efficient ferroelectric artificial synapse based on an oxide semiconductor and a SnCl 2 ‐incorporated P(VDF‐TrFE) gate dielectric layer. The synaptic performance of the device is significantly enhanced during the phase transition of the P(VDF‐TrFE) gate dielectric layer with the addition of SnCl 2 , resulting in an improved dynamic range (DR; from 6.63 to 145), nonlinearity (NL; from 2.75/3.24 to 0.74/2.49 for LTP/LTD), and weight‐update energy efficiency (from 95.65/−45.51 to 2669.04/−2573.53 A/J). Furthermore, the introduced ferroelectric artificial synapses exhibit high DR, low NL, and high energy efficiency update. The operation of the ferroelectric artificial synapse was successfully investigated using convolution neural network training sequences with the CIFAR‐10 dataset model, resulting in an 86% recognition accuracy.