Synchronised carrier-based SVPWM signal generation scheme for the entire modulation range extending up to six-step mode using the sampled amplitudes of reference phase voltages

The issues in synchronised implementation of space vector-based pulse width modulation (SVPWM) signal generation are addressed on a conventional DSP platform. With the present day digital signal processors (DSPs) with clock over 10 MHz, it is possible to include additional tasks for synchronisation in the interrupt service routine (ISR). Also, the task of the synchronisation can be easily accommodated within the same ISR without disturbing the time critical pulse width modulation (PWM) operation. The authors systematically present the additional software requirements to determine the time period proportional to the half carrier switching time interval that is required for the synchronisation. First, the DSP implementation of the conventional multi-level SVPWM based on the sampled amplitudes of reference voltages is presented and then the additional requirements to maintain the PWM in synchronisation are discussed. The simulation results as well as experimental results are presented for a five-level PWM signal generation. A five-level inverter configuration, using a 1.5 kW open-end winding induction motor drive, is used for experimentally verifying the SVPWM.